1. Field of the Invention
The invention relates to video compression and decompression techniques, more particularly to a video compressing apparatus and a video decompressing apparatus that perform a reduced number of multiplication operations.
2. Description of the Related Art
Discrete cosine transform (DCT) is widely adopted in video compression algorithms, such as MPEG for motion picture coding, and JPEG for still picture coding. Similarly, inverse discrete cosine transform (IDCT) is adopted in the corresponding inverse process for decompression of compressed video data.
DCT and IDCT operations typically involve a plurality of multiplication and addition operations. In general, multiplication operations for DCT and IDCT processing are relatively time-consuming and require relatively complex hardware.
In U.S. Pat. No. 5,471,412, the entire disclosure of which is incorporated herein by reference, the applicant disclosed six-stage DCT/IDCT fast algorithms that involve only thirteen multiplication operations for one-dimensional transformation, or a total number of 208 (2xc3x978xc3x9713) multiplication operations for two-dimensional transformation of an 8xc3x978 data block. It is desirable to further reduce the number of multiplication operations in order to achieve a higher processing speed during video compression and/or video decompression.
In co-pending U.S. patent application Ser. No. 09/153,750, now U.S. Pat. No. 6,160,920, the entire disclosure of which is also incorporated herein by reference, the applicant disclosed a cosine transforming and quantizing device, and an inverse quantizing and inverse cosine transforming device.
The cosine transforming and quantizing device comprises a discrete cosine transforming unit and a quantizer. The discrete cosine transforming unit performs discrete cosine transform (DCT) on an input data block based on a six-stage DCT fast algorithm. The discrete cosine transforming unit dispenses with a sixth intrinsic multiplication stage of the DCT fast algorithm to result in scaled transform data. The quantizer is connected to the discrete cosine transforming unit, and quantizes the scaled transform data in accordance with a modified quantizer matrix that is obtained by compensating a predetermined original quantizer matrix with a set of scaling coefficients derived from the sixth intrinsic multiplication stage of the DCT fast algorithm to result in quantized DCT data corresponding to the input data block. Through the use of the cosine transforming and quantizing device, the number of multiplication operations in a video compressing apparatus can be reduced to result in a higher processing speed.
The inverse quantizing and inverse cosine transforming device comprises an inverse quantizer and an inverse discrete cosine transforming unit. The inverse quantizer dequantizes input quantized discrete cosine transform (DCT) data in accordance with a modified dequantizer matrix that is obtained by compensating a predetermined original dequantizer matrix with a set of pre-scaling coefficients derived from a first intrinsic multiplication stage of a six-stage inverse discrete cosine transform (IDCT) fast algorithm to result in scaled dequantized data. The inverse discrete cosine transforming unit is connected to the inverse quantizer, and is operable to perform IDCT on the scaled dequantized data based on the six-stage IDCT fast algorithm. The inverse discrete cosine transforming unit dispenses with the first intrinsic multiplication stage of the IDCT fast algorithm to result in IDCT data corresponding to the input quantized DCT data. Through the use of the inverse quantizing and inverse cosine transforming device, the number of multiplication operations in a video compressing/decompressing apparatus can be reduced to result in a higher processing speed.
The object of the present invention is to provide a joint cosine transforming and quantizing device which has a relatively simple discrete cosine transforming unit that is capable of performing a reduced number of multiplication operations as compared to the prior art.
Another object of the present invention is to provide a joint inverse quantizing and inverse cosine transforming device which has a relatively simple inverse discrete cosine transforming unit that is capable of performing a reduced number of multiplication operations as compared to the prior art.
According to one aspect of the invention, a joint cosine transforming and quantizing device comprises a discrete cosine transforming unit and a quantizer.
The discrete cosine transforming unit performs discrete cosine transform (DCT) on an input data block based on a six-stage DCT fast algorithm that is separated into a scaled DCT stage and a scaling DCT stage. The scaled DCT stage includes a first butterfly stage, a second post-addition multiplication stage, a third butterfly stage, a fourth post-addition multiplication stage, and a fifth butterfly stage. The scaling DCT stage includes a sixth intrinsic multiplication stage. The discrete cosine transforming unit dispenses with the scaling DCT stage to result in scaled transform data.
The quantizer is connected to the discrete cosine transforming unit, and quantizes the scaled transform data in accordance with a modified quantizer matrix that is obtained by compensating a predetermined original quantizer matrix with a scaling coefficient matrix derived from the scaling DCT stage of the DCT fast algorithm to result in quantized DCT data corresponding to the input data block.
The discrete cosine transforming unit includes a data register unit, an input multiplexer, a butterfly operation unit, an adder and a multiplication operation unit.
The data register unit has first and second write ports and first and second read ports.
The input multiplexer has a first data input adapted to receive the input data block, a second data input connected to the first read port of the data register unit, and a data output. The input multiplexer is operable so as to provide data at a selected one of the first and second data inputs to the data output.
The butterfly operation unit has an input connected to the data output of the input multiplexer, and an output connected to the first write port of the data register unit. The butterfly operation unit is operable so as to perform the first, third and fifth butterfly stages of the DCT fast algorithm and so as to generate respectively first-stage, third-stage and fifth-stage output data when performing the first, third and fifth butterfly stages of the DCT fast algorithm.
The adder has a data input connected to the second read port of the data register unit, and a data output.
The multiplication operation unit has an input connected to the data output of the adder, and an output connected to the second write port of the data register unit.
The adder and the multiplication operation unit are operable so as to perform the second and fourth post-addition multiplication stages of the DCT fast algorithm and so as to generate respectively second-stage and fourth-stage output data when performing the second and fourth post-addition multiplication stages of the DCT fast algorithm.
The multiplication operation unit includes a look-up table and an output multiplexer.
The look-up table has a number of data fields, each of which contains products associated with a respective one of a corresponding number of coefficients used in the second and fourth post-addition multiplication stages of the DCT fast algorithm. The look-up table further has a number of outputs corresponding respectively to the data fields. The look-up table is connected to the data output of the adder so as to be addressed by data thereat in order to output the products, that correspond to the data from the adder and that are stored in the data fields, at the outputs of the look-up table.
The output multiplexer has data inputs connected to the outputs of the look-up table, and a data output connected to the second write port of the data register unit. The output multiplexer is operable so as to select one of the data inputs thereof and provide data at the selected one of the data inputs thereof to the data register unit.
According to another aspect of the invention, a joint inverse quantizing and inverse cosine transforming device comprises an inverse quantizer and an inverse discrete cosine transforming unit.
The inverse quantizer dequantizes input quantized discrete cosine transform (DCT) data in accordance with a modified dequantizer matrix that is obtained by compensating a predetermined original dequantizer matrix with a pre-scaling coefficient matrix derived from a pre-scaling inverse discrete cosine transform (IDCT) stage of a six-stage IDCT fast algorithm to result in scaled dequantized data. The pre-scaling IDCT stage includes a first intrinsic multiplication stage of the IDCT fast algorithm. The IDCT fast algorithm further has a scaled IDCT stage that includes a second butterfly stage, a third post-multiplication subtraction stage, a fourth butterfly stage, a fifth post-multiplication subtraction stage, and a sixth butterfly stage.
The inverse discrete cosine transforming unit is connected to the inverse quantizer and is operable to perform the scaled IDCT stage of the IDCT fast algorithm on the scaled dequantized data. The inverse discrete cosine transforming unit dispenses with the pre-scaling IDCT stage of the IDCT fast algorithm to result in IDCT data corresponding to the input quantized DCT data.
The inverse discrete cosine transforming unit includes a data register unit, an input multiplexer, a butterfly operation unit, a multiplication operation unit, and a subtracter.
The data register unit has first and second write ports and first and second read ports.
The input multiplexer has a first data input to receive the scaled dequantized data, a second data input connected to the first read port of the data register unit, and a data output. The input multiplexer is operable so as to provide data at a selected one of the first and second data inputs to the data output.
The butterfly operation unit has an input connected to the data output of the input multiplexer, and an output connected to the first write port of the data register unit. The butterfly operation unit is operable so as to perform the second, fourth and sixth butterfly stages of the IDCT fast algorithm and so as to generate respectively second-stage, fourth-stage and sixth-stage output data when performing the second, fourth and sixth butterfly stages of the IDCT fast algorithm.
The multiplication operation unit has a data input connected to the second read port of the data register unit and a data output.
The subtracter has an input connected to the data output of the multiplication operation unit, and an output connected to the second write port of the data register unit.
The multiplication operation unit and the subtracter are operable so as to perform the third and fifth post-multiplication subtraction stages of the IDCT fast algorithm and so as to generate respectively third-stage and fifth-stage output data when performing the third and fifth post-multiplication subtraction stages of the IDCT fast algorithm.
The multiplication operation unit includes a look-up table and an output multiplexer.
The look-up table has a number of data fields, each of which contains products associated with a respective one of a corresponding number of coefficients used in the third and fifth post-multiplication subtraction stages of the IDCT fast algorithm. The look-up table further has a number of outputs corresponding respectively to the data fields. The look-up table is connected to the second read port of the data register unit so as to be addressed by data thereat in order to output the products, that correspond to the data from the second read port and that are stored in the data fields, at the outputs of the look-up table.
The output multiplexer has data inputs connected to the outputs of the look-up table, and a data output connected to the input of the subtracter. The output multiplexer is operable so as to select one of the data inputs thereof and provide data at the selected one of the data inputs thereof to the subtracter.